The present invention is related to testing of logic circuit designs and, in particular, to compaction of test response data.
Testing of complicated digital logic circuits requires the analysis of a large amount of test response data. A variety of output compaction techniques have been devised for reducing the size of test response data stored in test memory. Most output compaction techniques use combinational circuits, predominantly built of exclusive-OR (XOR) networks, to reduce the number of scan channels that will be observed by automatic test equipment (ATE) during test applications. Unfortunately, such XOR-based output compactors disadvantageously can have decreased fault coverage caused by the masking of errors during a shift cycle. If there are an even number of scan flip-flops that drive the same XOR tree and are scanned out at the same shift cycle, then the errors are masked out and cannot be observed by the ATE. Likewise, a circuit under test (CUT) may produce unknown values during a simulation step that is required to compute output responses of the CUT to the applied stimuli. If an error is captured in a scan flip-flop that is scanned out at the same shift cycle as another scan flip-flop whose value is unknown and the two scan flip-flops drive the same XOR network, then the error again cannot be observed. A variety of sophisticated output compactors, implemented with complex arrays of XOR gates, have been devised to avoid error masking issues. See, e.g., S. Mitra and K. S. Kim, “X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction,” IEEE International Test Conference Proceedings, pp. 311-20 (October 2002); J. Rajski, K. Tyszer, C. Wang, S. M. Reddy, “Convolutional Compaction of Test Responses,” IEEE International Test Conference Proceedings, pp. 745-54 (September/October 2003); C. Wang, S. M. Reddy, I. Pomeranz, J. Rajski, J. Tyszer, “On Compacting Test Response Data Containing Unknown Values,” IEEE International Conference on Computer Aided Design, pp. 855-62 (November 2003). See FIG. 1A. Unfortunately, even such sophisticated output compactors, which use more XOR gates than a simple XOR tree, cannot avoid masking an even number of errors greater than two in a single shift cycle.
Synopsys's XDBIST has an output compactor that avoids the masking of errors by using a multiplexer instead of an XOR network to select scan chains that scan out errors. See P. Wohl, J. A. Waicukauski, S. Patel, “Scalable Selector Architecture for X-Tolerant Deterministic BIST,” IEEE 41st Design Automation Conference, pp. 934-939 (June 2004). See FIG. 1B. Although it can handle unknown values better than prior art XOR network-based output compactors, XBDIST's output compactor can only achieve a limited compression ratio and also requires additional test data to control the multiplexer and a special dedicated automatic test pattern generator (ATPG) that is compatible with the output compactor.
Accordingly, there is a need for improved test response compaction which can minimize issues such as the masking of faults.